Receiving data from interleaved multiple concurrent transactions in a FIFO memory

ABSTRACT

A FIFO memory receives data transfer requests before data is stored in the FIFO memory. Multiple concurrent data transfers, delivered to the FIFO memory as interleaved multiple concurrent transactions, can be accommodated by the FIFO memory (i.e., multiplexing between different sources that transmit in distributed bursts). The transfer length requirements associated with the ongoing data transfers are tracked, along with the total available space in the FIFO memory. A programmable buffer zone also can be included in the FIFO memory for additional overflow protection and/or to enable dynamic sizing of FIFO depth.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of the priority of U.S.Provisional Application Serial No. 60/339,643, filed Dec. 11, 2001 andentitled “PCI/X TRANSMIT FIFO”.

BACKGROUND

[0002] The present application describes systems and techniques relatingto first in first out (FIFO) memory design, for example, a FIFO designedto receive data over a bus from interleaved multiple concurrenttransactions.

[0003] In the field of FIFO memory design, addressing the potential forFIFO overflow and the resulting loss of data is a significant designconsideration. One traditional approach is to design the system and/ordevice in which the FIFO memory is to be placed such that data willalways be read out of the FIFO memory faster than the data is writteninto the FIFO memory.

[0004] Other conventional approaches include adding circuitry to theFIFO memory to output information relating to the current state of theFIFO memory. This information can then be used by external components inorchestrating data writing and reading, into and out of the FIFO memory.Typical examples of such FIFO state outputs include a full flag, anempty flag, an almost full flag and an almost empty flag. Additionally,some FIFO memories include circuitry that makes the almost full flagand/or the almost empty flag programmable.

SUMMARY

[0005] The present application teaches a FIFO memory with overflowprotection. According to an aspect, a FIFO memory receives data transferrequests before data is stored in the FIFO memory. Data transferrequests specify sizes of the data transfer to be initiated, to enabledetermination of whether the FIFO memory has enough space to accommodatethe data. Once a data transfer is initiated, the space in the FIFOmemory for that transfer can already be reserved by the transferrequest. Data can be asynchronously written into and read out of theFIFO memory.

[0006] Multiple concurrent data transfers, delivered to the FIFO memoryas interleaved multiple concurrent transactions, can be accommodated bythe FIFO memory (i.e., multiplexing between different sources thattransmit in distributed bursts). The transfer length requirementsassociated with the ongoing data transfers are tracked, along with thetotal available space in the FIFO memory. A programmable buffer zonealso can be included in the FIFO memory for additional overflowprotection and/or to enable dynamic sizing of FIFO depth.

[0007] One or more of the following advantages may be provided. Thesystems and techniques described may allow the use of a single FIFOmemory to receive data from interleaved multiple concurrent transactionsfor multiple data transfers, providing an effectively larger memorydepth than possible with separate FIFO memories, while still preventingFIFO overflow. Additionally, the systems and techniques described mayresult in the ability to dynamically size FIFO depth, making the FIFOmemory shareable, and a FIFO that can be tuned for various combinationsof write and read rates.

[0008] Details of one or more implementations are set forth in theaccompanying drawings and the description below. Other features andadvantages may be apparent from the description and drawings, and fromthe claims.

DRAWING DESCRIPTIONS

[0009] These and other aspects will now be described in detail withreference to the following drawings.

[0010]FIG. 1 is a block diagram illustrating a FIFO memory that receivestransfer length requests for multiple data transfers and authorizes datatransfers.

[0011]FIG. 2 is a block diagram illustrating a memory circuitryconfiguration that can be used in the FIFO memory of FIG. 1.

[0012]FIG. 3A is a combined flowchart and state diagram illustratingoperations performed in a FIFO memory that receives transfer lengthrequests for multiple data transfers and authorizes data transfers.

[0013]FIG. 3B is a flowchart illustrating configuring a FIFO memoryhaving a programmable buffer zone.

[0014]FIG. 4A is a block diagram illustrating a bus adapter.

[0015]FIG. 4B is a block diagram illustrating a host bus adapter cardaccording to one implementation.

[0016]FIG. 5 is a block diagram illustrating an example data processingsystem.

[0017]FIG. 6 is a block diagram illustrating an operational environmentfor a FIFO memory according to one implementation.

[0018] Like reference symbols in the various drawings indicate likeelements.

DETAILED DESCRIPTION

[0019] The systems and techniques described here relate to a FIFO memoryreceiving data from interleaved multiple concurrent transactions. Thedescription that follows frequently discusses FIFO memory in the contextof receiving data over a PCI-X (Peripheral Component InterconnectExtended) bus, but can be applied in other contexts.

[0020]FIG. 1 is a block diagram illustrating a FIFO memory 100 thatreceives transfer length requests for multiple data transfers andauthorizes data transfers. The FIFO memory 100 includes FIFO controlcircuitry 110 and FIFO memory circuitry 150. The FIFO control circuitry110 includes addressing logic enabling asynchronous read and writeoperations on the FIFO memory circuitry 150.

[0021] The addressing logic provides a write address 112 and a readaddress 114 to the FIFO memory circuitry 150. In addition, the FIFOcontrol circuitry 110 includes difference circuitry to track availablespace in the memory circuitry 150. This difference circuitry can includea storage location, such as a register, that holds a value indicatingeither the available space or the used space in the FIFO memorycircuitry 150. The difference circuitry can also include logic forgenerating and outputting a full flag on an output line 120 and anot_empty flag on an output line 122.

[0022] The FIFO memory 100 can accept data from interleaved multipleconcurrent transactions. These transactions correspond to multiplespecific data transfers, which may occur at different data rates. Thetransactions can be interleaved with respect to their corresponding datatransfers, such as by sending a first transaction corresponding to adata transfer A, a second transaction corresponding to a second datatransfer, a third transaction corresponding to the first data transfer,and a fourth transaction corresponding to the second data transfer. Forexample, in PCI-X, multiple data transfers, known as sequences, can beinitiated and received over a bus concurrently. A sequence in PCI-X isone or more data transactions associated with carrying out a singlelogical transfer by a requester, and these transactions can beprogrammed to run at 33, 66, 100, or 133 Mhz (Megahertz). Thus a requestfor one thousand bytes of data can be delivered all at once, or as smallbursts of varying size at varying times.

[0023] The FIFO memory 100 can accept data from these types ofinterleaved multiple concurrent transactions, while preventing FIFOoverflow. The FIFO control circuitry 110 includes two or more transferlength input lines 130, 132, 134. These transfer length input linesallow a reservation of FIFO space for an entire data transfer before thedata transfer is initiated. A ready output line 136 can be asserted whenthe sum of memory space requests does not exceed the available space inthe FIFO memory 100.

[0024] For example, a request line A 130 can receive a request for a1000 byte data transfer. This request A can be stored in the FIFOcontrol circuitry 110, and the difference circuitry compares thisrequest to the currently available space and any previously reservedspace. If the transfer data amount (1000 bytes) plus any previouslyreserved data amount is less than or equal to the available FIFO space,the request is authorized and the ready output line is asserted, therebyallowing initiation of the data transfer.

[0025] As data corresponding to request A is written into the FIFOmemory circuitry 150, the stored transfer data amount for request A isdecremented, indicating a reduction in the amount of space reserved inthe FIFO memory 100. When a second transfer request is received on arequest line B 132, the difference circuitry performs the same logicaloperations, where the stored transfer data amount for request A is partof the previously reserved data amount used in the comparison.

[0026] Thus, for read and write cycles, the FIFO control circuitry 110keeps track of the available space in the FIFO memory circuitry 150 andthe transfer length requirements associated with on-going datatransfers. Additionally, more than two request lines can be implemented,enabling more than two on-going data transfers with the correspondingmultiple concurrent transactions.

[0027] The FIFO control circuitry 110 may be programmable. In oneimplementation, the FIFO control circuitry 110 can be programmed torespond to requesters based on a strict first-come-first-serve rule, orthe FIFO control circuitry 110 can be programmed to use a modifiedfirst-come-first-serve rule where the first requester that does notexceed the current available space is the first served. Requesters thatare skipped can be kept track of in a register block, which may beeither internal or external to the FIFO memory 100.

[0028] The FIFO memory 100 may include controls forbig-endian/little-endian and byte-lane swapping. The FIFO memory 100 mayinclude test features to inject parity errors and force a FIFO overflowcondition. The FIFO memory 100 may include datacompression/decompression logic on its input and output respectively toprovide additional overflow protection.

[0029] The FIFO memory 100 enables overflow prevention by accepting datatransfer requests for FIFO resources and then outputting a ready flag toindicate whether the data transfer should be initiated. This can beuseful when receiving data over a bus in which data is delivered ininterleaved multiple concurrent transactions. For example, in PCI-X,data from multiple concurrent transactions can be written into a FIFOmemory in burst mode, where no wait state insertion may be allowed, andwhere the exact length of any one transfer may be unknown. In this typeof situation, multiple transactions with large amounts of data canarrive in rapid succession. This can cause FIFO overflow, unless thesemulti-transaction burst cycles are accommodated. The ready output line136 enables just-long-enough hold-off on data transfer requests duringasynchronous read and writes into the FIFO memory 100.

[0030] The FIFO control circuitry 110 also can include a buffer inputline 138 used to receive a programmable buffer zone size. Theprogrammable buffer zone size specifies an amount of the FIFO memory 100that is set aside. The buffer zone size can be stored in a register setin the FIFO memory 100. The buffer zone size can be included in thelogical operations performed by the difference circuitry to generate theready output, and can be included as part of the previously reservedamount or as unavailable space, depending on whether the buffer zoneshould be reflected in the full and not_empty outputs.

[0031] The buffer zone size can be programmed to a positive or negativevalue. A positive buffer zone size can be used to provide additionaloverflow prevention. This can be useful when the transfer data amountsreceived on the request lines do not exactly correspond to the amount ofdata that will be stored in the FIFO memory. For example, tagsidentifying which transaction particular data belongs to can be storedin data locations in the FIFO memory, as will be discussed furtherbelow.

[0032] The buffer zone size can be programmed to a negative value toallow greater amounts of data to be written into the FIFO memory 100. Anegative buffer zone causes the FIFO memory 100 to report more availablespace in the FIFO memory circuitry than is actually available. Thus, theFIFO memory 100 can be programmed to accommodate larger and more datatransfers without actually expanding the FIFO memory capacity.

[0033] The buffer zone size can be stored in a register set that isaccessible to external firmware. The bit patterns of this register setcan be programmed to enable a large variation in buffer zone size (i.e.,an eight bit register is not limited to representing a fixed set of twohundred and fifty six (2⁸) values). Reads from the FIFO memory 100 canbe made to run at various clock frequencies. Thus in someimplementations the difference in read and write speeds can be used toprotect against FIFO overflow. In such cases, a negative buffer zone canbe programmed to logically increase FIFO depth while still having anenforced upper limit, thus allowing FIFO memory sharing withsimultaneous control over overflow protection.

[0034] The FIFO memory circuitry 150 can be implemented using a dualport random access memory (RAM) or a register file. The FIFO memorycircuitry 150 includes a data input line 152, a write enable input line154, and a write clock input 156. The FIFO memory circuitry 150 alsoincludes read clock input 160 and a data output line 162. The FIFOmemory circuitry 150 can include storage locations for control bits anddata bits.

[0035] Moreover, the inputs and outputs of the FIFO memory 100 can beserial and/or parallel inputs/outputs. For example, the buffer inputline 138 can be an eight bit parallel input, and each of the transferlength input lines 130, 132, 134 can be a serial input line.

[0036]FIG. 2 is a block diagram illustrating a memory circuitryconfiguration that can be used in the FIFO memory of FIG. 1. A dual portRAM 200 includes control bits 210 and data bits 250. The control bits210 can be used to store tags identifying data transfers to which datastored in the data bits 250 corresponds (e.g., 5 bit PCI-X tags).

[0037] Alternatively, the control bits 210 can be used to identify databits 250 that are used to store tags. For example, control bits 212indicate that data bits 252 contain a data tag. In this fashion, datafor different transfers can be stored in the memory as they arereceived, and large tag values (e.g., 24 bit tags) can be stored withoutrequiring a large number of control bits. For example, control bits 212identify the beginning of data for a transaction, and data bits 252identify this transaction as belonging to data transfer A. Control bits214 identify the end of this data transaction. Control bits 216 identifythe beginning of data for another transaction, and data bits 256identify this transaction as belonging to data transfer B. Control bits218 identify the beginning of data for yet another transaction, and databits 258 identify this transaction as belonging to data transfer A.

[0038] When data tags are stored in the FIFO memory in this fashion, apositive buffer zone size can be used to prevent FIFO overflow. Forexample, in PCI-X, each transaction includes a tag that identifies thesequence to which the transaction belongs. A single sequence can be madeup of one transaction or multiple transactions. A positive buffer zonecreates room to account for storage of the variable number of tagsassociated with each sequence.

[0039] The dual port RAM 200 can be 1280×80. The control bits 210 can besixteen bits wide and the data bits 250 can be sixty-four bits wide. Thecontrol bits can include parity bits (e.g., eight parity bits, one foreach byte of data), valid bits (e.g., three valid bits specifying whichbytes of data are valid), and delimiter bits (e.g., four delimiter bitsspecifying whether the data bits contain a tag, data or the last word ofdata in a block, as well as possibly other information). The controlbits also can include an overflow status bit, which is set when writingdata with the full flag set. In this situation, error recovery can betriggered, and the overflow status bits can be used during errorrecovery.

[0040]FIG. 3A is a combined flowchart and state diagram illustratingoperations performed in a FIFO memory that receives transfer lengthrequests for multiple data transfers and authorizes data transfers. TheFIFO memory has an idle state 300. From this state 300, when a requestis asserted on a transfer length input line, a current transfer requestis received at 305. The current transfer request indicates a datatransfer length request. For example, a value indicating a requestedtransfer length can be latched into the FIFO memory.

[0041] Then, the current transfer amount in the request is compared witha previously reserved amount of FIFO space at 310. As discussed above,the previously reserved amount can include both reserve amounts for oneor more existing data transfers and an amount specified for a bufferzone. Next, retrieval of data for the current request is initiated, suchas by asserting a ready flag, only if the transfer amount plus thereserved amount (approved transfer request(s) plus any buffer space(positive or negative)) is less than or equal to the space available inthe FIFO memory.

[0042] As data is written into the FIFO memory, reserved FIFO spacecorresponding to the received data is decremented at 320. For example,the latched-in transfer length value corresponding to the data beingwritten into the FIFO memory is decremented in its storage location inthe FIFO memory. Also as data is written into the FIFO memory, theavailable FIFO space is decremented at 325. As data is read from theFIFO memory, the available FIFO space is incremented at 330.

[0043]FIG. 3B is a flowchart illustrating configuring a FIFO memoryhaving a programmable buffer zone. One or more data writing rates forinterleaved multiple concurrent transactions are identified at 350. Thiscan involve accessing a defined location where such data is stored,requesting such data, and/or receiving such data from another source.For example, in PCI-X, the possible data writing rates are defined bythe PCI-X standard. These writing rates, or a subset of these rates, canbe stored in firmware and/or software.

[0044] Next, one or more data reading rates are identified for data tobe read from a FIFO memory having a programmable buffer zone at 355. TheFIFO memory can be part of a system that includes a clock domain thatcan be made to run at various clock frequencies. In addition, the FIFOmemory can be read by multiple processors.

[0045] Finally, based on the identified one or more data writing ratesand the one or more data reading rates, the buffer zone size is set at360. This process allows dynamic sizing of FIFO depth and makes the FIFOmemory shareable. Because the FIFO memory's programmable buffer zone canbe specified as either a positive or a negative value, the FIFO memorycan effectively be tuned to work in various combinations of differentread and write data rates.

[0046]FIG. 4A is a block diagram illustrating a bus adapter 400. The busadapter provides an interface between a system-interconnect bus andstorage using a system-interconnect bus interface 407 and a storageconnection 417. The bus adapter 400 can be used to connect a computingsystem, such as a network server, to a storage area network, as will bediscussed further below. The bus adapter 400 includes a bus datatransmit FIFO 405, which includes the functionality described above.Thus, the system-interconnect bus can be a PCI-X bus that provides datatransfers using interleaved multiple concurrent transactions.

[0047] The bus adapter 400 can include management circuitry (not shown),including a transmit processor, coupled with the bus data transmit FIFO405. This management circuitry can coordinate the activities of the busdata transmit FIFO 405, providing an interface between the bus datatransmit FIFO 405 and the rest of the bus adapter 400, allowing transferof data from the system-interconnect bus interface 407 to other logicblocks that act on the data. For example, the transmit processor can beused to latch-in instructions to the bus data transmit FIFO 405,identifying to the bus data transmit FIFO 405 the length of data toobtain using the system-interconnect bus, a source memory address, and adestination address in a local memory 410. This management circuitryfunctionality also can be integrated into the FIFO 405.

[0048] When the bus data transmit FIFO 405 determines that it has enoughspace to handle a data transfer request, the bus data transmit FIFO 405requests the data transfer from a DMA (Direct Memory Access) arbitrator440, which controls access to the system-interconnect bus interface 407.When the DMA arbitrator 440 provides the system-interconnect businterface 407 to the FIFO 405, data is written into the FIFO 405.

[0049] Data is read out of the FIFO 405 and into the memory 410. Fromthe memory 410, data is written into a payload transmit FIFO 415, andthen read out of the FIFO 415 onto the storage connection 417 (e.g., asdata packets sent using a network interface). The storage connection 417can be part of a network interface connecting to a storage area network,such as a Fibre Channel storage area network.

[0050] Data can in turn be received over the storage connection 417 intoa payload receive FIFO 430 and transferred to the memory 410. This datacan then be written into a bus data receive FIFO 432 and read out of theFIFO 432 onto the system-interconnect bus interface 407.

[0051] The bus adapter 400 can be formed on a semiconductor substrate asan integrated circuit and can include various other components, such asa controller 420 for coordinating and orchestrating the activity of thebus adapter 400 and a register bus 422. Additionally, the bus adapter400 can be part of a larger system.

[0052]FIG. 4B is a block diagram illustrating a host bus adapter card450 according to one implementation. The host bus adapter card 450 isconfigured to be inserted into an existing computing system to providean interface to a storage area network, providing block-levelInput/Output (I/O) services. The host bus adapter 450 includes aprocessor 455, which can be an SA-110 StrongARM processor, provided byIntel Corporation, located at 2200 Mission College Boulevard Santa ClaraCalif. 95052-8119.

[0053] The host bus adapter 450 also includes a nonvolatile memory 460and a volatile memory 465. These memories can be used to storeinstructions for implementing the method described above. Thenon-volatile memory 460 can be a flash memory. The volatile memory 465can be a high-speed SRAM (Static Random Access Memory)-based memorydevice, such as a QDR (Quad Data Rate) SRAM with a dedicated read portand a dedicated write port. The volatile memory 465 can be used to storetransmit and receive payload data as well as to store network and buscontext information and processor data (e.g., code, stack and scratchdata).

[0054] The host bus adapter 450 also includes a bus adapter applicationspecific integrated circuit (ASIC) 470. This bus adapter ASIC 470connects the processor 455, the non-volatile memory 460 and the volatilememory 465 with a bus interface 475 and a network interface 480. The busadapter ASIC 470 can be implemented using various circuitry components,including those shown and described in connection with FIG. 4A above,and can be made to emulate the designs of multiple manufactures toimprove interoperability with various components to be connected to thehost bus adapter 450.

[0055] The bus interface 475 can be configured to connect with a PCI-Xbus. The network interface 480 can be configured to connect with a FibreChannel network.

[0056] The bus adapters shown and described above in connection withFIGS. 4A and 4B are presented as embodiments. Other bus adapters, aswell as entirely different devices, can use the systems and techniquesdescribed here. In general, a bus adapter provides I/O processing andphysical connectivity between a data processing system, such as aserver, and storage. The storage can be attached using a variety ofdirect attached or storage networking technologies, including FibreChannel, iSCSI (Small Computer System Interface over Internet Protocol),VI/IP (Virtual Interface over Internet Protocol), FICON (FiberConnection), or SCSI (Small Computer System Interface). A bus adapterprovides I/O processing capabilities, which reduces processing loads ona central processor in the data processing system to which the busadapter is attached.

[0057] In contrast, a network interface card typically relies heavily onthe central processor of a system for protocol processing, includingsuch functions as maintaining packet sequence order, segmentation andre-assembly, error detection and correction, and flow control. A busadapter manages entire I/O transactions with little or no involvement ofthe central processor in a system. In the example host bus adapter shownand described in FIG. 4B above, the host bus adapter includes aprocessor, a protocol controller ASIC, and buffer memory to maintaindata flow. This host bus adapter takes block-level data from a parallelI/O channel (e.g., PCI-X) and maps it to a routable protocol (e.g.,Fibre Channel).

[0058]FIG. 5 is a block diagram illustrating an example data processingsystem 500. The data processing system 500 includes a central processor510, which executes programs, performs data manipulations and controlstasks in the system 500. The central processor 510 can include multipleprocessors or processing units and can be housed in a single chip (e.g.,a microprocessor or microcontroller) or in multiple chips using one ormore printed circuit boards and/or other inter-processor communicationlinks (i.e., two or more discrete processors making up a multipleprocessor system).

[0059] The central processor 510 is coupled with a system-interconnectbus 515. The system-interconnect bus 515 provides one or more pathwaysthrough which data is transmitted among portions of the system 500. Thesystem-interconnect bus 515 can include multiple separate busses, whichcan be parallel and/or serial busses, bus interfaces, and/or busbridges. Each bus can have an address bus and a data bus. Thesystem-interconnect bus 515 can include an internal bus to connectinternal components to the central processor 510 and memory, and anexpansion bus to connect expansion boards and/or peripheral devices tothe central processor 510. The system-interconnect bus 515 includes atleast one bus architecture that allows data delivery using interleavedmultiple concurrent transactions, such as PCI-X, and can further includeany other known bus architecture (e.g., PCI, industry standardarchitecture (ISA), extended ISA (EISA), Accelerated Graphics Port(AGP), Universal Serial Bus (USB), SCSI, future bus architectures).

[0060] The data processing system 500 includes a memory 520, which iscoupled with the system-interconnect bus 515. The system 500 can alsoinclude one or more cache memories. These memory devices enable storageof instructions and data close to the central processor 510 forretrieval and execution.

[0061] The memory 520 can include a non-volatile memory and a volatilememory. For example, a non-volatile memory can be used to store systemfirmware, which can be used to handle initialization of the dataprocessing system 500 and loading of an operating system (OS), such asWindows® NT 4.0 Enterprise Edition, provided by Microsoft Corporation,located at One Microsoft Way Redmond Wash. 98052-6399. The volatilememory, which requires a steady flow of electricity to maintain storeddata, can be used to store instructions and data once the system 500starts up.

[0062] The data processing system 500 can include a storage device 530for accessing a medium 535, which is a machine-readable mediumcontaining machine instructions, such as instructions for causing thesystem 500 or components of the system 500 to perform operations. Themedium 535 can be removable and can include a boot media having OSinstructions and data that are loaded into the volatile memory when thesystem 500 boots up. The medium 535 can be read-only or read/write mediaand can be magnetic-based, optical-based, semiconductor-based media, ora combination of these. Examples of the storage 530 and the medium 535include a hard disk drive and hard disk platters, which may beremovable, a floppy disk drive and floppy disk, a tape drive and tape,and an optical disc drive and optical disc (e.g., laser disk, compactdisc, digital versatile disk).

[0063] The data processing system 500 can also include one or moreperipheral devices 540(1)-540(n) (collectively, devices 540), and one ormore controllers and/or adapters for providing interface functions. Thedevices 540 can be additional storage devices and media as describedabove, other storage interfaces and storage units, adaptors, inputdevices and/or output devices. For example, the system 500 can include adisplay system having a display device (e.g., a video display adapterhaving components for driving a display, including video random accessmemory (VRAM), buffer, and graphics engine).

[0064] The system 500 also includes a communication interface 550, whichallows software and data to be transferred, in the form of signals 554,between the system 500 and external devices, networks or informationsources. The signals 554 can be any signals (e.g., electronic,electromagnetic, optical) capable of being received on a channel 552(e.g., wire, cable, optical fiber, phone line, infrared (IR) channel,radio frequency (RF) channel, etc.). The signals 554 can embodyinstructions for causing the system 500 or components of the system 500to perform operations.

[0065] The communication interface 550 can be a communications port, atelephone modem or wireless modem. The communication interface 550 canbe a network interface card (e.g., an Ethernet card connected with anEthernet Hub), and may be designed for a particular type of network,protocol and channel medium, or may be designed to serve multiplenetworks, protocols and/or channel media.

[0066] Additionally, the system 500 includes a storage network interface560, which allows software and data to be transferred, in the form ofsignals 564, between the system 500 and a storage area network. Thesignals 564 can be any signals, such as the signals 554, capable ofbeing transmitted and received on a channel 562. The signals 564 canembody instructions for causing the system 500 or components of thesystem 500, such as the storage network interface 560, to performoperations. The storage network interface 560 can be a host bus adapter,such as shown and described in connection with FIG. 4B above.

[0067] When viewed as a whole, the system 500 is a programmable machine.Example machines represented by the system 500 include a server (e.g., anetwork host) a personal computer, a mainframe, and a supercomputer. Themachine 500 can include various devices such as embedded controllers,Programmable Logic Devices (PLDs) (e.g., PROM (Programmable Read OnlyMemory), PLA (Programmable Logic Array), GAL/PAL (Generic ArrayLogic/Programmable Array Logic)), Field Programmable Gate Arrays(FPGAs), ASICs, single-chip computers, smart cards, or the like.

[0068] Machine instructions (also known as programs, software, softwareapplications or code) can be stored in the machine 500, in the storagenetwork interface 560, and/or delivered to the machine 500 over acommunication interface. These instructions, when executed, enable themachine 500 to perform features and function described above. Theseinstructions represent controllers of the machine 500 and can beimplemented in a high-level procedural and/or object-orientedprogramming language, and/or in assembly/machine language. Suchlanguages may be compiled and/or interpreted languages.

[0069] As used herein, the term “machine-readable medium” refers to anycomputer program product, apparatus and/or device used to providemachine instructions and/or data to the machine 500, including amachine-readable medium that receives the machine instruction as amachine-readable signal. Examples of a machine-readable medium includethe medium 535 and the like, the memory 520, and/or PLDs, FPGAs, ASICs,and the like. The term “machine-readable signal” refers to any signal,such as the signals 554, used to provide machine instructions and/ordata to the machine 500.

[0070]FIG. 6 is a block diagram illustrating an operational environmentfor a FIFO memory according to one implementation. Multiple servers 600are connected with a storage area network. Each server 600 can beimplemented in the manner shown and described above. For example, aserver 600 can be an Intel® AC450NX System with four 550-MHz Pentium®III Xeon™ processors and 1 GB (Gigabyte) RAM, or a server 600 can be anIntel® OCPRF100 System with eight 550 MHz Pentium® III Xeon™ processorsand 1 GB RAM.

[0071] The storage area network includes multiple storage devices 610and a storage network 620. The storage network 620 can be a high-speednetwork dedicated to data storage. For example, the storage network 620can be a Fibre Channel network, such as a Fibre Channel Arbitrated Loopor a Fibre Channel Switched Fabric. Each storage device 610 can be astorage array using SCSI, PCI-X or other bus architecture, JBOD (Just aBunch of Disks), a RAID (Redundant Array of Inexpensive Disks)enclosure, or other mass storage device. In general, a storage device610 includes at least one machine-readable medium as defined above, andthe storage area network provides block-level I/O access to the sharedstorage devices 610 for the servers 600.

[0072] The servers 600 are connected with a network 630, which caninclude multiple machine networks, such as Ethernet networks, IP(Internet Protocol) networks and ATM (Asynchronous Transfer Mode)networks. The network 630 can be a private network, a virtual privatenetwork, an enterprise network, a public network, and/or the Internet.The network 630 provides a communication link between multiple clients640 and the servers 600.

[0073] Various implementations of the systems and techniques describedhere can be realized in digital electronic circuitry, integratedcircuitry, specially designed ASICs (application specific integratedcircuits), computer hardware, firmware, software, and/or combinationsthereof. The various implementations described above have been presentedby way of example only, and not limitation. Other systems,architectures, and modifications and/or reconfigurations of devices,machines and systems shown are also possible.

[0074] Other embodiments may be within the scope of the followingclaims.

What is claimed is:
 1. A method comprising: receiving a current transferrequest to store data in a first in first out (FIFO) memory, the data tobe retrieved using a bus, the current transfer request specifying atransfer amount for the data to be stored in the FIFO memory; andinitiating retrieval and storage of the data into the FIFO memory, onlyif the transfer data amount combined with a previously reserved dataamount has a predetermined relationship with an available FIFO space. 2.The method of claim 1, wherein the previously reserved amount comprisesa reserved FIFO space corresponding to a previous transfer request, themethod further comprising: decrementing the reserved FIFO space as datacorresponding to the previous transfer request is received and stored inthe FIFO memory; decrementing the available FIFO space as data iswritten into the FIFO memory; and incrementing the available FIFO spaceas data is read out of the FIFO memory.
 3. The method of claim 2,wherein the FIFO memory stores tags to distinguish stored datacorresponding to the previous transfer request from stored datacorresponding to the current transfer request.
 4. The method of claim 3,wherein the previously reserved amount further comprises a programmableFIFO buffer zone.
 5. The method of claim 4, wherein the programmableFIFO buffer zone is programmed to a negative value for FIFO memorysharing, and the predetermined relationship is that the transfer dataamount plus the previously reserved data amount is less than or equal tothe available FIFO space.
 6. The method of claim 4, wherein the buscomprises a system-interconnect bus.
 7. The method of claim 6, whereinthe system-interconnect bus comprises a Peripheral ComponentInterconnect Extended bus.
 8. A method comprising: identifying one ormore data writing rates for data to be received from interleavedmultiple concurrent transactions and written into a FIFO memory having aprogrammable buffer zone; identifying one or more data reading rates fordata to be read from the FIFO memory; and setting a buffer zone size forthe programmable buffer zone of the FIFO memory based upon theidentified one or more data writing rates and the one or more datareading rates.
 9. The method of claim 8, wherein identifying one or moredata writing rates comprises identifying one or more data writing ratesfor data to be received over a system-interconnect bus.
 10. The methodof claim 9, wherein setting the buffer zone size comprises setting thebuffer zone size to a negative number.
 11. The method of claim 10,wherein identifying one or more data reading rates comprises identifyingtwo or more data reading rates.
 12. The method of claim 11, wherein thesystem-interconnect bus comprises a Peripheral Component InterconnectExtended bus.
 13. The method of claim 12, wherein said identifying oneor more data writing rates and said identifying one or more data readingrates comprises identifying default rates.
 14. A first in first outmemory comprising: memory circuitry; and control circuitry coupled withthe memory circuitry, the control circuitry including differencecircuitry to track available space in the memory circuitry, transferlength input lines to receive memory space requests for multiple datatransfers, and a ready output line to indicate whether a sum of thememory space requests exceeds the available space.
 15. The memory ofclaim 14, wherein the memory circuitry includes control bits and databits.
 16. The memory of claim 15, wherein the control circuitry furtherincludes one or more buffer input lines to receive a buffer zone size,and wherein the ready output line indicates whether a sum of the memoryspace requests and the buffer zone size exceeds the available space. 17.The memory of claim 16, further comprising data compression circuitryand data decompression circuitry.
 18. The memory of claim 16, whereinthe control circuitry further includes a register set to hold thereceived buffer zone size, wherein the register set includesprogrammable bit patterns to designate large variations in buffer zonesize.
 19. The memory of claim 16, wherein the memory circuitry comprisesa dual port random access memory.
 20. Circuitry comprising: means forreceiving a current transfer request to store data in a FIFO memory, thedata to be retrieved using a bus, the current transfer requestspecifying a transfer amount for the data to be stored in the FIFOmemory; and means for initiating retrieval and storage of the data intothe FIFO memory, only if the transfer data amount plus a previouslyreserved data amount is less than or equal to an available FIFO space.21. The circuitry of claim 20, further comprising means for storing tagsto distinguish stored data corresponding to a previous transfer requestfrom stored data corresponding to a current transfer request.
 22. Thecircuitry of claim 21, further comprising means for programming a FIFObuffer zone.
 23. The circuitry of claim 22, further comprising means forcompressing and decompressing data.
 24. A bus adapter comprising: aprocessor; an adapter memory coupled with the processor; a bus interfacecoupled with the adapter memory through a first in first out memory, thebus interface supporting multiple concurrent data transfers; a storageconnection coupled with the adapter memory; the first in first outmemory coupled with the bus interface and with the adapter memory, thefirst in first out memory comprising memory circuitry, and controlcircuitry including difference circuitry to track available space in thememory circuitry, transfer length input lines to receive memory spacerequests for multiple data transfers, one or more buffer input lines toreceive a buffer zone size, and a ready output line to indicate whethera sum of the memory space requests and the buffer zone size exceeds theavailable space; and management circuitry coupled with the first infirst out memory, the management circuitry to provide the memory spacerequests to the transfer length input lines and coordinate initiation ofthe multiple data transfers.
 25. The bus adapter of claim 24, whereinthe memory circuitry includes control bits and data bits to store tagsidentifying data transactions stored in the memory circuitry.
 26. Thebus adapter of claim 25, wherein the bus interface conforms to aPeripheral Component Interconnect Extended bus standard.
 27. The busadapter of claim 26, wherein the storage connection comprises a networkinterface conforming to a Fibre Channel standard.
 28. The bus adapter ofclaim 27, wherein the management circuitry comprises a register block tostore memory space requests that are skipped by the first in first outmemory.
 29. The bus adapter of claim 28, wherein the first in first outmemory further comprises data compression circuitry and datadecompression circuitry.
 30. A system comprising: a programmable machineincluding a system-interconnect bus that supports interleaved multipleconcurrent transactions; a storage area network; and a bus adaptercoupled with the system-interconnect bus and the storage area network,the bus adapter comprising a processor, an adapter memory coupled withthe processor, a bus interface coupled with the system-interconnect busand coupled with the adapter memory through a first in first out memorycomprising memory circuitry, and control circuitry including differencecircuitry to track available space in the memory circuitry, transferlength input lines to receive memory space requests for multiple datatransfers, and a ready output line to indicate whether a sum of thememory space requests exceeds the available space.
 31. The system ofclaim 30, wherein the memory circuitry includes control bits and databits to store tags identifying data transactions stored in the memorycircuitry.
 32. The system of claim 31, wherein the control circuitryfurther includes one or more buffer input lines to receive a buffer zonesize, and wherein the ready output line indicates whether a sum of thememory space requests and the buffer zone size exceeds the availablespace.
 33. The system of claim 32, wherein the control circuitry furtherincludes a register set to hold the received buffer zone size, whereinthe register set includes programmable bit patterns to designate largevariations in buffer zone size.
 34. The system of claim 32, wherein thesystem-interconnect bus comprises a Peripheral Component InterconnectExtended bus.
 35. The system of claim 32, wherein the storage areanetwork comprises a Fibre Channel network and a plurality of massstorage devices.